Agile Secure Element IP

Customisable Security Enclave for Secure SoC Integration

Crypto Quantique’s Agile Secure Element IP is a pre-integrated, configurable security subsystem for embedding trust at the heart of your silicon. With a secure microprocessor, hardware cryptographic engines, and support for secure boot, key storage, and trusted execution, it forms a flexible and certifiable security boundary for your next-generation SoC.

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For teams building secure ASICs & SoCs with tight area and power budgets

  • SoC & ASIC Design Teams
    Embed a ready-to-certify secure zone in silicon without bespoke development.
  • Security Engineers
    Implement crypto, attestation, and key storage in hardware with fine control.
  • System Integrators
    Build trust into heterogeneous, multi-core, or subsystem-based SoCs.
  • Compliance & QA
    Streamline certification processes with modular IP and documentation.

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Integrated Secure Processor

Includes an optional RISC-V core for security-critical code isolation and lifecycle control

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Crypto-Accelerated

Built-in symmetric, asymmetric, and post-quantum crypto engines for high-speed operations

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Customisable Architecture

Configure features like secure boot, attestation, storage, and interfaces to fit your SoC

Ready for Regulation

Supports security features required by the CRA, ISO/SAE 21434, IEC 62443, and Common Criteria

Modular IP Delivery

Delivered as composable RTL with interface flexibility; APB, AXI, or AXI-Lite supported.

Faster Time to Market

Integrate a ready-to-certify secure zone without building a custom TEE or secure island from scratch

Secure Microprocessor Subsystem

Includes an embedded RISC-V core optimized for isolated execution of key management, attestation, and policy enforcement functions.

Built-In Crypto Engines

Accelerates AES, SHA2/3, ECC, and PQC algorithms (Kyber, Dilithium, SPHINCS+) with side-channel and fault-injection protection.

Secure Boot and Storage

Supports verified boot and cryptographic measurement with options for persistent key storage and sealing using on-chip PUF or OTP.

Interface Flexibility

Connects to host via standard SoC interconnects (APB, AXI, AXI-Lite) and integrates seamlessly into CPU clusters or peripheral zones.

Remote Attestation & PCRs

Provides attestation registers (PCRs) and reporting mechanisms to verify device state to local or remote verifiers.

Post-Quantum Ready

Includes hardware-ready implementations of PQC primitives to support long-lifecycle secure products and future-proof designs.

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Secure RISC-V Core

Trusted control of security lifecycle, attestation, and policy execution

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Embedded Crypto Primitives

Includes AES, ECC, SHA, Ascon, and optional PQC accelerators

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MARS Register Support

Incorporates DP, PCR, and FSM structures for TCG-compliant attestation

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RTL + IP Config Pack

Delivered with full RTL, test benches, integration docs, and timing constraints

Interface Support

Choose from APB4, AXI4, or AXI-Lite to match your SoC architecture

Key Storage Options

Use OTP, SRAM PUF, or secure registers for persistent identity

Standard Compliance

Built to support CRA, FIPS, ISO/IEC, and automotive-grade design flows

Scalable Footprint

Configure features to optimize area, latency, and performance trade-offs

Looking to integrate a pre-certified secure element IP into your next SoC?

Talk to Crypto Quantique experts today to learn more or start your evaluation.

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